verilog-generator 是做什么的？
Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
Agent skill for Verilog-2001 RTL generation and FPGA design workflows.
verilog-generator is a Claude Code agent skill that agent skill for Verilog-2001 RTL generation and FPGA design workflows.
npx skills add Eriemon/verilog-generatorAgent skill for Verilog-2001 RTL generation and FPGA design workflows.
ElevenLabs text-to-speech with mac-style say UX.
Oracle CLI second-model review/debug/refactor/design with selected files, dry-run token checks, API or browser engine.
Capture and automate macOS UI with the Peekaboo CLI.
You MUST use this before any creative work - creating features, building components, adding functionality, or modifying behavior. Explores user intent, requirements and design before implementation.
Prisma ORM patterns for TypeScript backends — schema design, query optimization, transactions, pagination, and critical traps like updateMany returning count not records, $transaction timeouts, migrate dev resetting the DB, @updatedAt skipped on bulk writes, and serverless connection exhaustion.
Django + Celery async task patterns — configuration, task design, beat scheduling, retries, canvas workflows, monitoring, and testing. Use when adding background jobs, scheduled tasks, or async processing to a Django app.